All members of the Pentium processor family are designed for mainstream desktops and provide significant improvements over previous generations of Intel Microprocessors, such as the Intel486^TM and Intel386^TM processors, while remaining binary compatible. Features include:

• 64-bit data bus
• Data integrity features
• Multiprocessor Interrupt Controller on-chip
• Performance monitoring and execution tracing
• SL technology power management features
• Memory page size feature
• A superscalar architecture capable of executing two integer instructions in parallel in a single clock, achieving up to two times the integer performance relative to an equivalent frequency Intel486 CPU.
• A pipelined Floating-Point Unit (FPU) for supporting the 32- and 64- formats specified in the IEEE standard 754, as well as an 80-bit format. It is capable of executing two floating-point instructions in a single clock, achieving over five times the floating-point performance with instruction scheduling and overlapped (pipelined) execution.The FPU is object-code compatible with the Intel486 DX and Intel 487 SX, Intel 387 DX, and Intel 387 SX math coprocessors.
• Many instructions microcoded in earlier x86 processors are now hardwired for increased performance.
• Bus control signals for maintaining cache consistency in multiprocessor systems.
• Multiprocessor interrupt controller on-chip, enabling low-cost symmetric multiprocessing.
• Dual processor mode which provides a performance boost for applications running under advanced 32-bit operating systems.
• An extended form of paging provides access to data structures larger than the available memory space by keeping them partly in memory and partly on disk.
• Hardware support for virtual interrupts provided through the Virtual Interrupt Flag (VIF) and Virtual Interrupt Pending (VIP) bits in the EFLAGS register eliminate the need to trap to a monitor from the virtual-8086 or protected modes for certain operations.
• CPU identification for providing family, model, stepping and feature information with the CPUID instruction. The capability of executing this instruction is determined by the ability to set the ID bit in the EFLAGS register.
• Error Detection of internal devices and the external bus interface provided through parity protection and a Machine Check Exception (MCE). Hardware support is also provided to verify bus cycle completion.

Several features are used for testing, and performance monitoring. These features include:

• Built-In Self Test (BIST), providing 100% single stuck-at fault coverage of the microcode and large PLA's as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLB's) and constant ROM's.
• IEEE 1149.1 Standard Test Access Port and Boundary Scan architecture mechanism, allowing testing of the Pentium processor through a standard interface.
• Debug Extensions which allow debugging of I/O addresses, as well as memory access.
• Internal counters that can be used for performance monitoring and event counting.

Notes: 1 Performance comparisons are based on 200 MHz Pentium processor with MMX technology vs. 200 MHz Pentium processor.

2 Based on standard benchmarks:CPUmark16, CPUmark32, Norton SI32, SPECint95, SPECfp95, SysMarkNT, Sysmark32, Sysmark95.

Since the Pentium processor with MMX technology's debut, Intel has released an even more powerful microprocessor, the Pentium® II processor, running at speeds of up to 400MHz.

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